Search results for "Programmable logic device"
showing 10 items of 10 documents
Optimal implementation of neural activation functions in programmable logic using fuzzy logic
2006
Abstract This work presents a methodology for implementing neural activation function in programmable logic using tools from fuzzy logic. This methodology will allow implementing these intrinsic non-linear functions using comparators and simple linear modellers, easily implemented in programmable logic. This work is particularized to the case of a hyperbolic tangent, the most common function in neural models, showing the excellent results yielded with the proposed approximation.
Smart Cooling System for Milk Transportation in Rural Areas
2021
In the dairy industry, road milk tankers transport milk from one location to another. The milk inside the tanker needs to be kept between 3–5 °C to ensure that the quality of milk is always preserved. The tanker needs to be kept running at all time with the case of sufficient energy being continuously supplied to the cooling unit. The source of energy normally used for this application is a typical generator which needs fuel to operate. This is expensive and is not environmentally friendly. To address this problem, generator as a source of energy needs to be replaced by solar energy to lower the costs associated with cooling of the tanker. In this research a small scale solar powered intell…
A reconfigurable architecture for autonomous visual-navigation
2003
This paper describes the design of a reconfigurable architecture for implementing image processing algorithms. This architecture is a pipeline of small identical processing elements that contain a programmable logic device (FPGA) and double port memories. This processing system has been adapted to accelerate the computation of differential algorithms. The log-polar vision selectively reduces the amount of data to be processed and simplifies several vision algorithms, making possible their implementation using few hard-ware resources. The reconfigurable architecture design has been devoted to implementation, and has been employed in an autonomous platform, which has power consumption, size a…
FPGA-based embedded Logic Controllers
2014
In general case, reconfigurable logic controllers (RLC) are included into reactive digital embedded systems, carrying out control for several processes proceeding concurrently. The paper presents a practical application of a formal, rule-based specification language in Gentzen sequent logic, which is used as an intermediate textual description of a control interpreted Petri net. On the other hand exactly the same description serves also as logic design expressions, related with different versions of functionally equivalent concurrent state machine models, considered on Register Transfer Level. The symbolic rule-based specification of Petri net-based embedded Logic Controllers (LCs) can be s…
Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses Control of a PMSM
2021
This work examines the FPGA programmable logic platforms applied to minimum losses control of a Permanent Magnet Synchronous Motor (PMSM), which represents a flexible solution for the implementation of an advanced digital control algorithm, given their intrinsic parallel structure and the capability to be directly reprogrammable in the field. In particular, design and validation of a FPGA-based Hardware-In-the-Loop (HIL) simulator is proposed, by investigating about data format, quantization and discretization effects and other issues arising during the experimental validation of a controller prototype, in order to reduce the embedded software development cycle and test control systems. The…
Remote, web-based laboratory for Programmable Logic Devices
2009
Abstract This work proposes a web-based laboratory for remotely testing FPGA programs on an evaluation board. Using a web browser, the user can download a device configuration file (previously generated with the FPGA commercial tool) and test it in a real FPGA board located in a remote laboratory at the University facilities. The user can control inputs and check outputs’ state. This preliminary study tries to evaluate the possibilities that can be offered to the user, and the restrictions that might apply. Additionally, it describes the proposed infrastructure (hardware and software) needed to successfully deal with all the interesting features that a remote lab system for programmable log…
Reconfigurable digital instrumentation based on FPGA
2004
A novel application of FPGA to realize digital test equipment is proposed. It takes advantage of the dynamic reconfigurability of FPGAs so easily tailoring custom test functions in the same instrument. This results in high effective, compact and low cost instruments.
A readout unit for high rate applications
2002
The LHCb readout unit (RU) is a custom entry stage to the readout network of a data-acquisition or trigger system. It performs subevent building from multiple link inputs toward a readout network via a PCI network interface or alternatively toward a high-speed link, via an S-link interface. Incoming event fragments are derandomized, buffered and assembled into single subevents. This process is based on a low-overhead framing convention and matching of equal event numbers. Programmable logic is used both in the input and output stages of the RU module, which may be configured either as a data-link multiplexer or as entry stage to a readout or trigger network. All FPGAs are interconnected via…
High performance hardware correlation coefficient assessment using programmable logic for ECG signals
2003
Abstract Correlation coefficient is frequently used to obtain cardiac rhythm by peak estimation and appreciate differences in the signal compared to a pattern. This work focuses on the description of a real-time correlation assessment procedure. Applied to electrocardiogram (ECG) signals, a new correlation value is obtained every new sample and pulse detection information is provided. The ECG pattern is internally stored and can be changed when desired. This procedure is useful in Systems on Chip implementation and can be applied to design compact ECG monitoring systems consisting on a system on chip where programmable logic offloads the main processor. A Xilinx FPGA device has been used fo…
A hardware skin-segmentation IP for vision based smart ADAS through an FPGA prototyping
2017
International audience; In this paper we presents a platform based design approach for fast HW/SW embedded smart Advanced Driver Assistant System (ADAS) design and prototyping. Then, we share our experience in designing and prototyping a HW/SW vision based smart embedded system as an ADAS that helps to increase the safety of car's drivers. We present a physical prototype of the vision ADAS based on a Zynq FPGA. The system detects the fatigue state of the driver by monitoring the eyes closure and generates a real-time alert. A new HW/SW codesign skin segmentation step to locate the eyes/face is proposed. Our presented new approach migrates the skin segmentation step from processing system (S…